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quad 8-bit, 65 msps, serial lvds 3 v a/d converter ad9289 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features four adcs in o n e package serial lvds dig i tal output dat a rates to 5 20 mbps (ansi-64 4) data an d fram e clock outputs snr = 48 dbc (to nyquist) excellent linea r ity dnl = 0.2 lsb (typical) inl = 0.25 ls b (typical) 300 mh z fu ll p o wer analog bandwidth power dissipati o n = 112 m w /channel at 6 5 m s ps 1 vp-p to 2 vp- p input voltage range 3.0 v supply op eration power-down mode digital tes t pat t ern enable for timing alignme n ts applic ati o ns tape dri v es medical imagin g func tio n a l block di agram ad9289 8 8 8 8 vin+a vin ?a d1+a d1? a sha pipeline adc serial lvds data rate multiplier ref select vin+b vin ?b d1+b d1? b sha pipeline adc serial lvds vin+c vin ?c d1+c d1? c sha pipeline adc serial lvds vin+d vin ?d vref sense d1+d d1? d 0.5v fco+ lock fco? dco+ dco? sha pipeline adc serial lvds reft_a refb_a reft_b refb_b agnd clk+ clk? lvdsbias cml shared_ref avdd dfs pdwn dtp drvdd drgnd 03682-001 fi g u r e 1 . produc t d e scripti o n the ad9289 is a q u ad 8-b i t, 65 ms ps a n alog-t o - dig i tal con v er - t e r (ad c ) wi t h a n o n -ch i p s a m p le-an d -h ol d ci r c ui t t h a t is desig n e d f o r lo w cos t , lo w p o w e r , smal l size , and e a s e o f us e . the p r o d uc t op era t es a t u p t o a 65 ms ps con v ersio n ra t e and is o p t i mi ze d fo r o u tst a ndin g d y namic p e r f o r ma n c e w h er e a sma l l p a cka g e si z e is cr i t ica l . the a d c r e q u i r es a sin g le , 3 v p o w e r s u p p l y a nd a n l v ds- co m p a t i b le s a m p le ra t e c l o c k f o r f u l l p e r f o r ma nce o p era t ion. n o ext e r n al r e fer e n c e o r dr i v er co m p on e n ts a r e r e q u ir e d fo r m a n y ap p l i c at i o n s . the a d c a u t o ma t i c a l l y m u l t i p lies t h e s a m p le ra t e clo c k fo r t h e a p p r o p ria t e l v d s se ri al d a ta ra t e . a d a ta c l oc k ( d co ) f o r ca pt ur in g d a t a o n t h e o u t p u t and a f r am e clo c k (fc o ) t r ig ger fo r sig n a l in g a ne w o u t p ut b y t e a r e p r o v ide d . p o w e r - do w n is s u p p o r t e d . th e ad c typ i cal l y c o n s u m es 7 mw w h en enab le d . f a b r ica t ed on an ad van c e d cm os p r o c es s, the ad9289 is a v a i la b l e in a 64 -bal l mini-b ga p a c k a g e (64-b g a). i t is s p e c if ie d o v er t h e i n d u s t r i al t e m p er a t ur e ra n g e o f C40c t o +85c. product highlights 1. f o u r a d c s are c o n t ai n e d i n a s m a l l, sp a c e - s a v i ng p a ck ag e. 2. a d a t a clo c k o u t (d c o ) is p r o v ide d , w h ich op e r a t es u p t o 260 mh z and su p p o r ts do u b le-da t a r a t e op era t io n (d d r ). 3. t h e output s of e a ch a d c are s e r i a l i z e d l v d s w i t h d a t a ra t e s u p t o 520 mb ps (8 b i ts 65 ms ps). 4. the ad9289 o p era t es f r o m a sin g le 3.0 v p o w e r s u p p l y . 5. t h e in t e rn al c l o c k d u t y c y c l e s t a b iliz e r m a i n t a in s p e r f o r ma n c e o v er a wide ra n g e o f in p u t clo c k d u ty c y cles.
ad9289 rev. 0 | page 2 of 32 table of contents specifications..................................................................................... 3 ac specifications.......................................................................... 4 digital specifications ................................................................... 4 switching specifications .............................................................. 5 timing diagrams.......................................................................... 5 absolute maximum ratings............................................................ 6 explanation of test levels........................................................... 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 equivalent circuits ........................................................................... 8 typical performance characteristics ..............................................9 terminology .................................................................................... 12 theory of operation ...................................................................... 14 analog input and reference overview ................................... 14 clock input and considerations .............................................. 15 evaluation board ............................................................................ 20 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 10/04initial version: revision 0
ad9289 rev. 0 | page 3 of 32 specifications avdd = 3.0 v, drvdd = 3.0 v, conversion rate = 65 msps, 2 v p-p differential input, 1.0 v internal reference, ain = C0.5 dbfs, unless otherwise noted. table 1. parameter temperature test level min typ max unit resolution 8 bits accuracy no missing codes full vi guaranteed offset error full vi 5 57 mv offset matching full vi 12 68 mv gain error 1 full vi 0.5 2.5 % fs gain matching 1 full vi 0.2 0.9 % fs differential nonlinearity (dnl) 25c v 0.2 lsb full vi 0.2 0.6 lsb integral nonlinearity (inl) 25c v 0.25 lsb full vi 0.25 0.6 lsb temperature drift offset error full v 16 ppm/c gain error 1 full v 40 ppm/c reference voltage (vref = 1 v) full v 10 ppm/c reference output voltage error (vref = 1 v) full vi 10 35 mv load regulation @ 1.0 ma (vref = 1 v) full v 0.7 mv output voltage error (vref = 0.5 v) full vi 8 26 mv load regulation @ 0.5 ma (vref = 0.5 v) full v 0.2 mv input resistance full v 7 k? common mode common-mode level output full vi 1.5 50 mv analog inputs differential input voltage range (vref = 1 v) full vi 2 v p-p differential input voltage range (vref = 0.5 v) full vi 1 v p-p common-mode voltage full v 1.5 v input capacitance full v 5 pf analog bandwidth, full power full v 300 mhz power supply avdd full iv 2.7 3.0 3.3 v drvdd full iv 2.7 3.0 3.3 v iavdd 2 full vi 150 168 ma drvdd 2 full vi 33 40 ma power dissipation 2 full vi 550 625 mw power-down dissipation full vi 7 12 mw crosstalk full v C75 db 1 gain error and gain temperature coefficients are based on the adc only (with a fixed 1.0 v external reference and a 2 v p-p di fferential analog input). 2 power dissipation measured with rated encode and 2.4 mhz analog input at C0.5 dbfs.
ad9289 rev. 0 | page 4 of 32 ac specifications avdd = 3.0 v, drvdd = 3.0 v, conversion rate = 65 msps, 2 v p-p differential input, 1.0 v internal reference, ain = C0.5 dbfs, unless otherwise noted. table 2. parameter temperature test level min typ max unit signal-to-noise ratio (snr) f in = 2.4 mhz full iv 47.7 49.0 db f in = 10.3 mhz 25c v 48.5 db f in = 35 mhz full vi 46.7 48.0 db signal-to-noise ratio (sinad) f in = 2.4 mhz full iv 47.6 48.9 db f in = 10.3 mhz 25c v 48.4 db f in = 35 mhz full vi 46.2 47.5 db effective number of bits (enob) f in = 2.4 mhz full iv 7.6 7.8 bits f in = 10.3 mhz 25c v 7.7 bits f in = 35 mhz full vi 7.4 7.6 bits spurious-free dynamic range (sfdr) f in = 2.4 mhz full iv 61.0 70.0 dbc f in = 10.3 mhz 25c v 68.0 dbc f in = 35 mhz full vi 54.0 65.0 dbc worst harmonic (second or third) f in = 2.4 mhz full iv C75.0 C61.0 dbc f in = 10.3 mhz 25c v C70.0 dbc f in = 35 mhz full vi C65.0 C54.0 dbc worst other (excluding second or third) f in = 2.4 mhz full iv C70.0 C61.0 dbc f in = 10.3 mhz 25c v C68.0 dbc f in = 35 mhz full vi C65.0 C57.5 dbc two tone intermod distortion (imd) ain1 and ain2 = C7.0 dbfs f in1 = 15 mhz f in2 = 16 mhz 25c v C72.0 dbc digital specifications avdd = 3.0 v, drvdd = 3.0 v, conversion rate = 65 msps, 2 v p-p differential input, 1.0 v internal reference, ain = C0.5 dbfs, unless otherwise noted. table 3. parameter temperature test level min typ max unit clock inputs 1 (clk+, clkC) logic compliance lvds differential input voltage full iv 250 350 450 mv p-p high level input current full vi 30 75 a low level input current full vi 30 75 a input common-mode voltage full iv 1.125 1.25 1.375 v input resistance 25c v 100 k? input capacitance 25c v 2 pf logic inputs (dfs, pdwn, shared_ref) logic 1 voltage full iv 2.0 v logic 0 voltage full iv 0.8 v input resistance 25c v 30 k? input capacitance 25c v 4 pf logic outputs ( lock ) logic 1 voltage full iv 2.45 v logic 0 voltage full iv 0.05 v digital outputs (d1+, d1C) logic compliance lvds differential output voltage full vi 260 350 440 mv output offset voltage full vi 1.15 1.25 1.35 v output coding full vi twos complement or binary 1 clock inputs are lvds-compatibl e. they require external dc bias and cannot be ac-coupled.
ad9289 rev. 0 | page 5 of 3 2 switchi n g specificati o ns a v d d = 3.0 v , d r vd d = 3.0 v , co n v ersio n ra te = 65 ms ps, 2 v p-p dif f er en t i al in p u t, 1.0 v in t e r n al r e f e r e n c e , ain = C0.5 db fs, unles s ot he r w i s e note d . table 4. p a r a m e t e r t e m p t e s t leve l m i n t y p m a x u n i t c l o c k maximum clock rate full vi 65 msps minimum clock rate full iv 12 msps clock pulse wid t h high (t eh ) f u l l v i 6 . 9 7 . 7 n s clock pulse wid t h low (t el ) f u l l v i 6 . 9 7 . 7 n s o u tput pa ram e ters val i d time (t v ) 1 f u l l i v 0 . 5 < 1 . 5 c l k c y c l e s propagation de l a y (t pd ) full vi 6.9 9.0 11.6 ns rise time (t r ) (2 0% to 80%) full v 250 ps fall t ime ( t f ) (20 % to 80%) full v 250 ps fco propagatio n delay (t fc o ) full v 9.0 ns dco propagatio n delay (t cpd ) f u l l v 9 . 0 n s dco-to-data delay (t dat a ) f u l l v i 1 0 0 5 5 0 p s dco-to-fco del a y (t fr a m e ) f u l l v i 1 0 0 5 0 0 p s data-to-data skew (t dat a -max C t dat a -min ) f u l l i v 1 0 0 2 5 0 p s pll lock time (t lock ) 2 5 c v 1 . 8 s wake-up time 25c v 7 ms pipeline latency full iv 6 clk cycles apertu r e aperture delay ( t a ) 25c v 4.5 ns aperture uncertainty (j itter) 25c v <1 ps rms out-of-range recovery t i me 25c v 1 clk cycles 1 a c tual val i d time i s d e p e nd e nt o n the mo me nt whe n lock go es low. timing diagrams lock dco ? dco+ d1? d1+ fco? fco+ clk ? ain clk+ n- 1 n t eh t cpd t data t v t frame msb (n -7 ) d6 (n -7 ) d5 (n -7 ) d4 (n -7 ) d3 (n -7 ) d2 (n -7 ) d1 (n -7 ) ls b (n -7 ) ms b (n -6 ) t fco t pd t el t a 03682-003 static static static invalid static static static f i g u re 2. ti ming d i ag r a m
ad9289 rev. 0 | page 6 of 3 2 absolute maximum ratings table 5. parameter with respect to min max unit electr i c a l a v d d a g n d C 0 . 3 + 3 . 9 v d r v d d d r g n d C 0 . 3 + 3 . 9 v a g n d d r g n d C 0 . 3 + 0 . 3 v a v d d d r v d d C 3 . 9 + 3 . 9 v digital outputs ( d 1 + , d1C, dc o+, dc o C , fco+, fcoC) d r g n d C 0 . 3 dr vd d v lock , lvdsbias d r g n d C 0 . 3 dr vd d v clk+, clkC agnd C0.3 avdd v vin+, vinC agnd C0.3 avdd v pdwn, dfs, d t p agnd C0.3 avdd v reft, refb, shared_r ef, c m l a g n d C 0 . 3 a v d d v vref, sen s e agnd C0.3 avdd v environ m en t a l operating temperature range (ambient) C 4 0 + 8 5 c maximum junction temperature 1 5 0 c lead temperature (sol dering, 10 s e c) 3 0 0 c storage temperature range (ambient) C 6 5 + 1 5 0 c thermal impedance 1 4 0 c / w explanation of test levels i. 100% p r o d uc tion t e st ed . ii. 100% p r o d uc tion t e st ed a t 25c a nd gua r an t e ed b y desig n a nd cha r ac ter i z a t i o n a t sp e c if ie d te m p er a t ur es. iii. s a m p l e te ste d on ly . iv. p a r a me te r i s g u ar an te e d b y d e s i g n a n d ch ar a c te r i z a t i on te st i n g . v. p a ra m e t e r is a typ i cal val u e o n ly . vi. 100% p r o d uc tion t e st ed a t 25c a nd gua r an t e ed b y desig n a n d c h a r a c t e riza ti o n f o r in d u s t ri al t e m p era t ur e ra n g e . s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . 1 ja for a 4- la yer pc b wi t h so li d groun d pla n e i n st i ll a i r . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad9289 rev. 0 | page 7 of 3 2 pin conf iguration and fu nction descriptions 03682-005 h g f e d c b a 1 234 567 8 f i gure 3. bg a t o p view (l ook i ng th r o ugh) ta ble 6. pi n f u nct i on d e s c ri pt i o ns pin no. m n e m o n i c d e s c r i p t i o n a1 d1Ca adc a comp lem e nt digital ou tp ut b1 d1 +a adc a tr ue dig i t a l output c1 fco+ frame cl oc k output (msb indi c a tor) true output d1 dn c do n o t c o n n ect e 1 a g n d analog grou n d f1 vinCa adc a a n alog i n putcomp l eme n t g1 vin+a adc a a n alog i n puttrue h 1 l v d s b i as 1 lvds out p ut bia s pin a2 dn c do n o t c o n n ect b2 dn c do n o t c o n n ect c2 fcoC frame cl oc k output (msb indi c a tor) compl e ment ou tput d2 dn c do n o t c o n n ect e 2 a g n d analog grou n d f 2 a v d d analog sup p l y g 2 a g n d analog grou n d h2 vin+b adc b a n alog in puttrue a3 d1Cb adc b comp lem e nt digital ou tp ut b3 d1 +b adc b tr ue dig i ta l output c 3 d r vd d dig i ta l supp l y d 3 d r gn d dig i ta l gr o u n d e 3 a g n d analog grou n d f3 cml common mode level output ( = avd d /2) g3 share d _ref 3 shared referenc e control bit h3 vinCb adc b a n alog in putcomp l eme n t a4 dn c do n o t c o n n ect b4 dn c do n o t c o n n ect c4 dco+ data clock out p uttrue d4 lock pll lo ck output e 4 a v d d analog sup p l y f4 reft _a referenc e buffer d e c o u p l i ng (p osi t ive) g4 refb_a referenc e buffer d e c o u p l i ng (negative) h 4 s e n s e referenc e mode sel e c t i o n a5 d1Cc adc c complement digital ou tp ut b5 d1 +c adc c tr ue dig i t a l output c 5 d c o C da ta c l oc k out p utcompleme n t pin no. m n e m o n i c d e s c r i p t i o n d 5 a g n d analog grou n d e 5 a g n d analog grou n d f5 reft _b referenc e buffer d e c o u p l i ng (p osi t ive) g5 refb_b referenc e buffer d e c o u p l i ng (negative) h5 vref vol t age reference input/output a6 dn c do n o t c o n n ect b6 dn c do n o t c o n n ect c 6 d r vd d dig i ta l supp l y d 6 d r gn d dig i ta l gr o u n d e 6 a v d d analog sup p l y f 6 a g n d analog grou n d g 6 a g n d analog grou n d h 6 vinCc ad c c ana l og inputcompl eme n t a7 d1C d adc d c o m p lem e nt dig i ta l ou tp ut b7 d1 +d adc d tr ue dig i t a l output c 7 d f s 2 data format sele ct d 7 a g n d analog grou n d e 7 a g n d analog grou n d f 7 a v d d analog sup p l y g 7 a g n d analog grou n d h 7 vin+ c ad c c ana l og inputt rue a8 dn c do n o t c o n n ect b8 dn c do n o t c o n n ect c 8 c l k + input clock t r u e d 8 clkC input clock compl e ment e 8 p d w n 3 po wer do wn se l e ction f8 vinCd adc d analog in putcomp l eme n t g8 vin+ d ad c d analog inputt rue h8 dt p 3 , 4 digital test patte rn 1 lvds bia s use a 3.9 k ? re s i s t o r -to -anal o g gro u nd to se t the lvds o u tput differential swin g of 350 mv p-p. 2 d f s h a s a n i n t e rn a l on - c h i p pull- down resi st or a n d de fa ult s t o of fs et bi n a ry o u tput co d i ng if un tie d . if twos co mp l e me nt o u tput co d i ng is d e s i red the n tie this pin to a v dd . 3 to e n abl e , tie this pin to a v dd. to d i sabl e , tie this pin to a g nd. 4 d t p h a s a n i n t e rn al on - c h i p pull- down re si st or.
ad9289 rev. 0 | page 8 of 3 2 equivalent circuits avdd agnd vin+, vin ? 03682-006 f i g u re 4. equ i v a l e n t a n al og input c i rc uit avdd 375 ? agnd c lk+, cl k ? 03682-007 f i gure 5. e q u i v a len t clock input cir c uit drvdd 375 ? drgnd dfs, pdwn, shared_ref 03682-008 f i gure 6 . e q ui v a lent di gi tal input c i r c ui t drvdd drgnd d1 ? d1+ v v 03682-009 v v f i gure 7 . e q ui v a lent di gi tal o u tput circui t lock 03682-010 drvdd drgnd 25 ? fi g u r e 8 . e q u i v a l e n t lo c k o u tput circuit
ad9289 rev. 0 | page 9 of 3 2 typical perf orm ance cha r acte ristics frequency (mhz) amp l i t ude (dbfs ) 0 ?20 ?40 ?60 ?80 ? 100 0.0 4.1 12.2 8.1 20.3 16.3 24.4 28.4 32.5 03682-014 a i n = ? 0.5d bf s snr = 49 .08d b enob = 7.86 bits sfdr = 70.55d bc f i gure 9. s i ngl e - t o n e 3 2 k fft with f in = 2. 4 m h z, f sa mple = 65 m s ps frequency (mhz) amp l i t ude (dbfs ) 0 ?20 ?40 ?60 ?80 ? 100 0.0 4.1 12.2 8.1 20.3 16.3 24.4 28.4 32.5 03682-015 a i n = ?0.5d bf s snr = 48.93d b enob = 7.83 bits sfdr = 71.45d bc f i g u re 10. sing l e - t one 3 2 k fft w i t h f in = 1 0 . 3 mh z, f sa mpl e = 65 msps frequency (mhz) amp l i t ude (dbfs ) 0 ?20 ?40 ?60 ?80 ? 100 0.0 4.1 12.2 8.1 20.3 16.3 24.4 28.4 32.5 03682-016 a i n = ? 0.5d bf s snr = 48.8d b enob = 7.8 bits sfdr = 68.5d bc f i g u re 11. sing l e - t one 3 2 k fft w i t h f in = 3 5 m h z, f sa mple = 6 5 ms p encode (msps) db 75 70 60 65 55 50 45 10 20 40 30 60 50 70 03682-017 ain = ? 0.5dbfs 2v p-p, snr (db) 2v p-p, sfdr (dbc) 1v p-p, snr (db) 1v p-p, sfdr (dbc) f i gure 12. snr/sf d r vs. f sa mple , f in = 2. 4 mh z encode (msps) db 75 70 60 65 55 50 45 10 20 40 30 60 50 70 03682-018 ain = ? 0.5dbfs 2v p-p, snr (db) 1v p-p, snr (db) 2v p-p, sfdr (dbc) 1v p-p, sfdr (dbc) f i gure 13. snr/sf d r vs. f sa mple , f in = 1 0 . 3 mh z encode (msps) db 75 70 60 65 55 50 45 10 20 40 30 60 50 70 03682-019 ain = ? 0.5dbfs 2v p-p, snr (db) 2v p-p, sfdr (dbc) 1v p-p, snr (db) 1v p-p, sfdr (dbc) f i gure 14. snr/sf d r vs. f sa mple , f in = 3 5 mh z
ad9289 rev. 0 | page 10 of 32 2v p-p, snr (db) 2v p-p, sfdr (dbc) 1v p-p, snr (db) 1v p-p, sfdr (dbc) 70db reference line analog input level (dbfs) db 75 60 40 30 50 20 10 0 ?4 0 ? 3 5 ?2 5 ?3 0 ? 1 0 ?1 5 ?2 0 ? 5 0 03682-020 f i gure 15. snr/sf d r vs. a n alog inp u t l e vel , f sa mple = 6 5 m s ps, f in = 2 . 4 m h z 2v p-p, snr (db) 2v p-p, sfdr (dbc) 1v p-p, snr (db) 1v p-p, sfdr (dbc) 70db reference line analog input level (dbfs) db 75 60 40 30 50 20 10 0 ?4 0 ? 3 5 ?2 5 ?3 0 ? 1 0 ?1 5 ?2 0 ? 5 0 03682-021 f i gure 16. snr/sf d r vs. a n alog inp u t l e vel , f sa mple = 6 5 m s ps, f in = 1 0 . 3 mh z 2v p-p, snr (db) 2v p-p, sfdr (dbc) 1v p-p, snr (db) 1v p-p, sfdr (dbc) 70db reference line analog input level (dbfs) db 75 60 40 30 50 20 10 0 ?4 0 ? 3 5 ?2 5 ?3 0 ? 1 0 ?1 5 ?2 0 ? 5 0 03682-022 f i gure 17. snr/sf d r vs. a n alog inp u t l e vel , f sa mple = 6 5 m s ps, f in = 3 5 m h z sfdr (dbc) snr (db) frequency (mhz) db 75 70 60 55 65 50 45 0.1 1 1 0 100 03682-023 f i gure 18. snr/sf d r vs. f in , f sa mple = 6 5 mh z frequency (mhz) amp l i t ude (dbfs ) 0 ?20 ?40 ?60 ?80 ? 100 0.0 4.1 12.2 8.1 20.3 16.3 24.4 28.4 32.5 03682-024 a i n 1 and a i n 2 = ? 7 . 0 d bf s s f d r = 69.9d b c i m d 2 = 7 4 . 9d bc i m d 3 = 7 2 . 9d bc f i g u re 19. t w o - t o n e 3 2 k fft wit h f in 1 = 1 5 m h z and f in 2 = 16 mh z, f sa mple = 65 msps sfdr (dbc) 70db reference line analog input level (dbfs) db 80 70 40 50 30 60 20 10 0 ?4 0 ? 3 5 ?2 5 ?3 0 ? 1 0 ?1 5 ?2 0 ? 5 0 03682-025 f i gure 20. t w o - t o n e sfdr v s . a n al og i n put l e vel w i th f in 1 = 1 5 m h z and f in2 = 1 6 m h z, f sa m p le = 65 msps
ad9289 rev. 0 | page 11 of 32 temperature ( c) db 75 70 60 65 55 50 45 ? 4 0 ? 20 20 06 0 49 80 03682-026 2v p-p, sinad (db) 1v p-p, sinad (db) 2v p-p, sfdr (dbc) 1v p-p, sfdr (dbc) f i gure 21. sinad/ s f dr vs. t e mper ature , f sa mple = 65 msp s , f in 1 0 .3 mh z temperature ( c) gain e rror (ppm/ c) 15 10 0 5 ?5 ?10 ?15 ? 4 0 ? 20 20 06 0 49 80 03682-027 shared ref mode (pin tied high) shared ref mode (pin tied low) f i gure 22. g a in v s . t e m p er ature code dnl (ls b ) 0.5 0.4 0 0.1 0.2 0.3 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 0 3 2 128 96 64 192 160 224 256 03682-028 f i g u re 23. t y pic a l d n l, f in = 2. 4 m h z, f sa m p l e = 65 msp s code inl (lsb) 0.5 0.4 0 0.1 0.2 0.3 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 0.5 0 3 2 128 96 64 192 160 224 256 03682-029 f i g u re 24. t y pic a l i n l, f in = 2. 4 m h z, f sa m p l e = 65 msp s
ad9289 rev. 0 | page 12 of 32 terminology ana l og b a n d w i d t h ana l og b a n d wi d t h is t h e ana l og in p u t f r e q uenc y a t w h ich t h e s p ectral po w e r o f th e fun d a m en tal f r eq uen c y (a s d e t e rm in e d b y th e fft anal ysis) is r e d u ced b y 3 db f r o m f u l l s c ale . ap e r t u r e d e l a y a p er t u r e del a y i s a m e asur e o f t h e s a m p le- a n d - h old am plif ier (s h a ) p e r f o r ma n c e an d is m e as ur ed f r o m the 50% p o in t r i sing e d ge o f t h e clo c k in p u t t o t h e t i m e a t w h ich t h e in p u t sig n a l is hel d for c o n v e r s i on . ap e r t u r e un c e r t a i n t y ( j i t t e r ) a p er t u r e ji t t er is t h e va r i a t ion i n a p er t u r e dela y fo r s u cces s i v e s a m p l e s a n d c a n b e m a n i fe ste d a s f r e q u e nc y - d e p e nd e n t noi s e on t h e a d c i n put . c l o c k pu ls e w i d t h and d u ty cy cl e pulse w i d t h h i g h i s th e m i ni m u m a m o u n t o f tim e tha t t h e c l ock p u ls e s h o u l d b e lef t in t h e l o g i c 1 s t a t e t o achi e v e a ra te d p e r f o r ma n c e. pu ls e wi d t h lo w is t h e m i ni m u m t i me t h e clo c k p u ls e s h o u l d b e lef t in t h e lo w s t a t e . a t a g i v e n c l o c k ra te , th es e sp e c if ic a t ion s d e f i n e an acc e p t ab le clo c k d u ty c y cle. cr o s s t alk cr osst a l k is def i n e d as t h e co uplin g o f a cha n nel w h en a l l ch an nel s are d r i v e n b y a f u l l - s c a l e s i g n a l . d i f f erenti a l a n a l o g i n put c a p a c i t a nc e the co m p lex i m p e dance sim u la te d a t e a ch a n a l o g in p u t p o r t . d i f f erenti a l a n a l o g i n put v o lt a g e r a ng e the p e a k -t o - p e ak dif f er en t i al vol t a g e t h a t m u st b e a p plie d t o t h e con v er t e r t o g e n e r a t e a f u l l - s cale r e s p o n s e . p e ak dif f er en t i a l v o l t a g e is com p u t e d b y obs e r v i n g t h e v o l t a g e on a p i n and s u b t rac t in g t h e v o l t a g e f r o m a s e co nd p i n tha t is 180 o u t o f p h a s e . p e a k - t o-peak d i f f e r e n ti a l i s co m p u t ed b y r o ta ti n g t h e i n p u t p h a s e 180 a n d ta ki n g t h e peak m e as ur em en t a g a i n . th e dif f er en ce is com p u t e d b e tw e e n b o t h p e a k m e as ur emen t s . d i f f erenti a l n o n l i n e a r i ty ( d n l , n o mi s s i n g c o d e s ) a n i d eal a d c exh i b i t s co d e tra n si ti o n s tha t a r e e x a c tl y 1 l s b a p a r t. dnl is t h e de v i a t io n f r o m t h is ide a l va lue . g u a r an t e e d n o mis s in g co des to a n 8-b i t r e s o l u tio n indic a t e s t h a t al l 256 co des, r e s p e c t i v e l y , m u s t b e p r es en t o v er al l o p era t in g ra n g es. e f f e c t iv e n u mb er of b i ts (eno b) f o r a sin e w a v e , s i n a d can b e exp r es s e d i n t e r m s o f t h e n u m b er o f b i ts. u s in g t h e f o l l o w in g f o r m u l a , i t is p o s s i b le t o ob t a i n a m e as ure o f p e r f o r ma n c e exp r es s e d as n , t h e ef fe c t i v e nu m b e r o f b i t s : n = (s in ad C 1.76)/6.02 th us, t h e ef fe c t i v e n u m b er o f b i ts fo r a de vice fo r sin e w a v e in p u ts a t a g i ve n in p u t f r e q ue nc y ca n b e ca lc u l a t e d dir e c t ly fr o m i t s m e a s u r e d s i n a d . ga in er r o r the la rgest gain er r o r is sp e c if ie d an d is con s ide r e d t h e dif f er en ce b e twe e n t h e m e a s ur e d and ide a l f u l l - s c a l e i n p u t vol t age r a ng e. ga in m a t c h i n g e x pre s s e d i n % f sr . c o m p ut e d u s i n g t h e f o l l ow i n g e q u a t i o n : % 100 2 min max min max ? ? ? ? ? ? + ? = fsr fsr fsr fsr ng gainmatchi w h er e fsr ma x i s th e m o s t posi ti v e ga i n e r r o r o f th e a d cs, a n d fsr min i s th e m o s t n e ga ti v e ga in e r r o r o f th e ad c s . s e c o n d a n d t h i r d ha r m on i c d i s t or t i on the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e s e c o nd or t h i r d h a r m on i c c o m p one n t , re p o r t e d i n d b c . i n t e g r a l n o nlin ea ri ty (inl) inl r e f e rs t o the de via t io n o f e a c h in di vid u al c o de f r o m a lin e dr a w n f r o m nega t i ve f u l l s c a l e t h r o ug h p o si t i ve f u l l s c a l e t h e p o in t us ed as nega ti v e f u l l s c ale o c c u rs 1/2 ls b bef o r e the f i rs t co de t r a n s i t i o n . p o si t i ve f u l l s c a l e is def i ne d as a le vel 1 1/2 l s b b e yo nd t h e la st co de t r a n s i t i o n . the d e v i a t ion is m e a s ur e d f r o m th e mi d d le o f eac h pa r t i c ula r cod e t o th e tr ue s t ra i g h t lin e . off s et e r r o r the la rg es t o f fs et er r o r is s p e c if ie d and is co n s i d er e d t h e dif f er en ce b e twe e n t h e m e as ur e d and ide a l v o l t a g e a t t h e a n al og i n p u t th a t p r od uce s th e m i d s ca le cod e a t th e o u t p u t s.
ad9289 rev. 0 | page 13 of 32 offset matching expressed in mv. computed using the following equation: offsetmatching = off max ? off min where off max is the most positive offset error and off min is the most negative offset error. out-of-range recovery time out-of-range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. output propagation delay the delay between the clock logic threshold and the time when all bits are within valid logic levels. signal-to noise and distortion (sinad) ratio sinad is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious-free dynamic range (sfdr) sfdr is the difference in db between the rms amplitude of the input signal and the peak spurious signal. temperature drift the temperature drift for offset error and gain error specifies the maximum change from the initial (25c) value to the value at t min or t max . two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. it may be reported in dbc (i.e., degrades as signal levels are lowered) or in dbfs (always related back to converter full scale).
ad9289 rev. 0 | page 14 of 32 theory of operation e a c h a/d con ver t e r in the ad9289 a r c h i t ec t u r e co n s is ts o f a f r o n t s e nd s a m p le-an d -h ol d a m plif ier (s h a ) fol l o w e d b y a p i pe- l in ed , sw i t c h ed ca pa c i t o r a d c . th e p i pe li n e d a d c i s divide d i n to two s e c t io n s , co n s i s t i n g o f six 1.5- b i t st a g es an d a f i na l 2-b i t f l a s h. e a ch st a g e p r o v ides suf f i cie n t o v erla p t o co r r e c t fo r f l as h er r o rs i n t h e p r e c e d in g s t a g es. the q u an t i ze d o u t p u t s f r o m eac h s t a g e a r e co m b in e d in t o a f i nal 8 - b i t r e s u l t in t h e dig i t a l co r r e c -tio n log i c. th e p i p e lin e d a r c h i t e c t u r e p e r m i t s the f i rs t s t a g e t o o p era t e on a ne w i n p u t s a m p le , w h i l e t h e r e ma inin g s t a g es o p era t e o n p r e c e d in g s a m p les. sa m p l i n g o c c u rs o n th e r i sin g edg e o f t h e c l o c k. e a ch s t a g e o f t h e p i p e li n e , excl udin g t h e last, co n s is ts o f a lo w re s o lut i on f l a s h a d c c o n n e c te d to a s w i t c h e d c a p a c i tor di g i t a l - to - a na l o g c o n v e r te r ( d a c ) and i n te rs t a ge re s i du e am pl i f i e r (md a c). the md a c ma g n if i e s t h e dif f er en c e b e tw e e n t h e r e co n s tr uct e d d a c o u t p u t a n d th e f l as h in p u t f o r th e n e xt s t a g e in t h e p i p e lin e . on e b i t o f r e d u ndan c y is us ed in eac h o f t h e s t a g es t o fac i li t a t e dig i t a l co r r e c t i o n o f f l as h er ro rs. th e l a s t st age s i m p ly c o ns ists of a f l as h a d c . the i n p u t st a g e co n t a i n s a dif f er en t i al s h a t h a t ca n b e conf ig- ur e d as ac- o r d c -co u ple d i n d i f f er en t i a l o r sin g le-ende d m o des . the o u t p u t -s t a g i n g b l o c k alig n s t h e da t a and c a r r i es o u t t h e er r o r co r r e c t i o n . th e d a t a is s e r i a l iz e d and a l ig ne d to t h e f r a m e, o u t p ut clo c k, and lo ck de te c t ion cir c ui t r y . analog input and re ference overview the a n alog in pu t t o t h e a d 928 9 is a dif f er en t i a l -s wi t c he d ca p a c i t o r s h a tha t has b e en de sig n e d fo r o p tim u m p e r f o r - ma nce w h i l e p r o c es sin g a dif f er en t i al i n p u t sig n al . the s h a in p u t can su pp or t a wid e co m m o n - m o d e r a n g e a nd ma i n t a in exce l l en t p e r f o r ma nce , as sh o w n in f i gur e 26 s a nd f i gur e 27. an in p u t co m m o n - m o d e vol t a g e o f midsu p ply mini mi zes s i g n a l d e p e nd e n t e r ror s and prov i d e s opt i m u m p e r f or m a nc e. 03682-051 h h vin+ vin ? c par c par s s s s f i g u re 25. swit che d - c apaci t o r s h a in put u p da te the clo c k sig n a l al t e r n a t e l y sw i t ch es t h e s h a b e tw e e n s a m p le m o de a n d h o l d m o de (see f i gur e 25). w h en th e s h a i s swi t ch e d in t o s a m p le m o de , t h e sig n al s o ur ce m u s t be ca p a b l e o f c h a r g i n g th e s a m p le c a p a ci t o rs a n d s e t t l i n g wi t h in one-half of a cl o c k c y cl e. a s m a l l res i stor in s e r i es wi t h e a ch in p u t c a n h e l p r e d u ce t h e p e ak t r a n sie n t c u r r en t r e q u ir e d f r o m t h e o u t p ut s t a g e o f t h e dr ivin g s o ur ce . als o , a smal l s h u n t c a p a ci t o r ca n b e pl ace d acr o ss t h e i n p u ts t o p r o v ide d y na mic cha r g i n g c u r r en ts. this p a s s i v e n e tw o r k cr e a t e s a lo w-p a s s f i l t er a t t h e ad c s i n p u t; t h er efo r e , t h e p r e c is e val u es a r e de p e nden t o n t h e ap p l i c at i o n . the a n alog in pu ts o f t h e ad92 89 a r e n o t in ter n al l y dc b i as e d . i n ac-co u ple d a p pl ica t ion s , t h e us er m u st p r o v ide t h is b i as ext e r - na l l y . s e t t i n g t h e de vic e s o t h a t v cm = av d d /2 is r e co mme n d e d f o r opt i m u m p e r f o r m a nc e, but t h e d e v i c e f u nc t i ons ove r a wider r a n g e wi t h r e as o n a b l e p e r f o r ma n c e (s e e f i gur e 26 a nd f i gur e 27). 2v p-p, sfdr (dbc) 2v p-p, snr (db) 1v p-p, snr (db) 1v p-p, sfdr (dbc) analog input common-mode voltage (v) db 75 70 60 50 55 65 45 40 35 0 0.5 1.0 2.0 1.5 2.5 3.0 03682-030 f i gure 26. snr, sfd r vs. c o mmon-m ode v o ltag e , f in = 2.4 mhz , f sa mple = 65 msps 2v p-p, sfdr (dbc) 2v p-p, snr (db) 1v p-p, snr (db) 1v p-p, sfdr (dbc) analog input common-mode voltage (v) db 75 70 60 50 55 65 45 40 35 0 0.5 1.0 2.0 1.5 2.5 3.0 03682-031 f i gure 27. snr, sfd r vs. c o mmon-m ode v o ltag e , f in = 3 5 mh z, f sa mple = 65 msps f o r b e st dy n a m i c p e r f or m a nc e, t h e s o u r c e i m p e d a nc e s d r iv i n g vin+ an d vin? s h o u ld b e ma tch e d s u ch t h a t c o mm on- m o d e s e t t ling er r o rs a r e symm et r i cal . th e s e er r o rs a r e r e d u ce d b y t h e c o m m on - m o d e re j e c t i o n of t h e a d c .
ad9289 rev. 0 | page 15 of 32 an in t e r n al r e fer e n c e b u f f er cr ea t e s t h e p o si t i v e a nd n e g a t i v e re f e re nc e vo lt ag e s , r e f t a n d r e f b , re sp e c t i vel y , t h a t d e f i ne s t h e s p an o f t h e ad c co r e . the o u t p ut co mm on- m o d e o f t h e r e fer e n c e b u f f er is s e t t o midsu ppl y , a n d t h e re ft an d refb vol t a g es and sp a n a r e def i n e d a s reft = 1/2 ( av d d + vref ) refb = 1/2 ( av d d ? vref ) sp a n = 2 ( re ft ? re fb ) = 2 vref i t ca n be seen f r o m th e eq ua ti o n s a b o v e tha t t h e r e ft a n d refb v o l t a g es ar e symm et r i cal a b o u t t h e midsu p pl y v o l t a g e a n d , b y d e f i n i tio n , th e i n p u t s p a n i s tw ice t h e val u e o f th e v r ef vol t age. the i n t e r n al v o l t a g e r e fer e n c e c a n b e p i n- s t ra pp e d t o f i xe d val u es o f 0.5 v o r 1.0 v o r ad j u s t ed wi thin t h e s a me ra n g e , as d i scu s sed i n t h e i n t e rn al r e f e r e n c e c o nn ecti o n secti o n . m a xim u m s n r p e r f o r ma n c e is ac hieved b y s e t t in g the ad9289 t o t h e l a rges t i n p u t s p an o f 2 v p-p . the s h a sh o u ld b e dr i v e n f r o m a s o ur ce t h a t k e eps t h e sig n al p e aks w i t h i n t h e al lo wa b l e ra n g e fo r t h e s e le c t e d r e fer e n c e vol t a g e. t h e mi nim u m and ma x i m u m com m on- m o d e i n p u t le vels a r e def i n e d in f i gur e 26 and f i gur e 27. differenti a l input config urations o p tim u m p e r f o r ma n c e is achie v ed b y dr i v in g t h e ad9289 in a dif f er en t i a l in put co nf igura t ion. f o r b a s e b a nd a p plica t io n s , t h e ad8351 dif f er en tial dr i v er p r o v ides exce l l en t p e r f o r ma n c e and a f l exi b le in t e r f ace t o t h e a d c ( s e e f i gur e 28). ad8351 gp1 v cm pwup gp2 1.2k ? 25 ? 1k ? 1k ? 10k ? 0.1 f 10 ? 1k ? 1k ? 03682- 054 ad9289 vin ? vin+ av dd a gnd r r c 0.1 f 0.1 f 1v p-p 10 ? 50 ? 25 ? 0.1 f 0.1 f avdd 1k ? 1k ? h o w e v e r , t h e no is e p e r f o r ma nce o f m o st am pl if iers is n o t adeq u a te t o ac hiev e t h e tr ue p e r f o r ma n c e o f the ad9289. f o r a p plic a t ion s w h er e s n r is a k e y p a ra m e ter , dif f er en t i a l t r a n sfo r - m e r co u p li n g is t h e r e co m m e n d e d i n p u t conf igura t io n. a n exa m p l e o f this is s h own in f i g u r e 29. i n an y co nf igur a t io n, t h e va l u e o f t h e s h u n t ca p a ci t o r , c, is d e p e nd e n t o n t h e i n put f r e q u e nc y a n d m a y ne e d to b e re d u c e d or re move d. 03682-053 ad9289 vin+ vin ? av dd a gnd 2 vp - p r r c 49.9 ? 0.1 f 1k ? 1k ? avdd f i g u re 29. d i f f e r e nt ia l t r ans f or mer - co upled conf ig u r at io n single-ended input configuration a sin g le-e nde d in p u t ma y p r o v i d e ade q u a te p e r f o r ma n c e i n cost-s en s i t i v e a p plica t io n s . i n t h is co nf igura t ion, t h er e is a deg r ad a t ion i n s f dr a nd di stor t i o n p e r f o r ma n c e d u e to t h e la rg e in pu t co mm on- m o d e s w i n g. h o w e v e r , if t h e s o ur ce im p e dan c es o n e a ch i n p u t a r e ma t c h e d , t h er e s h o u ld b e li t t le e f f e c t o n sn r p e r f or m a n c e . fi g u r e 3 0 d e t a i l s a t y pi c a l s i n g l e - en d e d i n p u t conf igur a t io n. 03682-052 2v p-p r r c 49.9 ? 0.1 f 10 f 10 f 0.1 f ad9289 vin+ vin? avdd agnd avdd 1k ? 1k ? 1k ? 1k ? t y p i cal hig h sp e e d ad cs us e b o th c l o c k e d g e s t o g e n e r a t e a va r i ety o f in ter n a l t i ming sig n a l s, a nd as a r e su lt ma y b e s e ns i t ive to cl o c k d u ty c y cl e. t y p i c a l l y , a 5 % tol e r a nc e is re q u ire d on t h e cl o c k d u ty c y cl e to main t a i n dy namic p e r f or - ma nce c h a r ac t e r i s t ics. th e ad9 289 has a s e lf-c o n ta ined c l o c k d u t y c y c l e s t a b ili z e r tha t r e tim e s th e n o n s a m p l in g ed g e , p r o v idin g an i n ter n a l clo c k sig n a l w i t h a n o min a l 50% d u ty c y cl e. this a l l o ws a wide r a nge of cl o c k in p u t d u ty c y cl es wi t h o u t a f f e c t ing th e p e r f o r ma n c e o f t h e ad9 289. an o n - b o a r d phas e-lo ck e d lo op (p ll) m u l t i p l i es t h e i n p u t clo c k ra t e fo r t h e p u r p os e o f s h if t i n g t h e s e r i al da t a o u t. a s a re su lt , an y ch a n ge to t h e s a m p l i ng f r e q u e nc y re qu i r e s a mini m u m o f 10 0 clo c k p e r i o d s to a l lo w t h e pl l to r e acq u ir e a nd lo ck to t h e ne w r a te.
ad9289 rev. 0 | page 16 of 32 h i g h s p e e d , hig h r e s o l u t i o n ad cs a r e s e n s i t i v e t o t h e quali t y o f t h e clo c k in p u t. the deg r a d a t ion in s n r a t a g i v e n f u l l -s c a le in p u t f r e q uen c y (f a ) du e on l y t o a p e r tu re j i tt e r ( t a ) ca n b e calcula t ed wi th th e f o llo w i n g e q ua ti o n : snr deg r ada t i o n = 20 log10 [ 1 /2 f a t a ] i n t h e e q ua t i o n , t h e r m s a p er t u re ji t t er , t a , r e p r es en ts t h e r o o t s u m s q ua r e o f a l l ji t t er s o ur ces, whic h in c l ude t h e c l o c k in p u t, a n a l og in p u t sig n a l , a nd a d c a p er t u r e ji t t er sp e c if ica t ion. a p plica t ion s t h a t r e q u ir e u n ders a m pling a r e p a r t ic u l a r ly s e ns i t iv e to j i tte r . the l v ds clo c k in p u t sh o u ld b e t r e a t e d as an a n a l og sig n a l in cas e s w h er e a p e r t u r e ji t t er ma y a f fe c t t h e dynamic ra n g e o f t h e ad9289. p o w e r s u p p lies f o r c l o c k dr i v ers sh o u ld b e s e p a ra t e d f r o m t h e ad c o u t p ut dr i v er s u p p lies t o a v o i d m o d u l a t i ng t h e clo c k sig n a l wi t h dig i t a l n o is e . l o w ji t t er , cr ysta l-co n t r o l l e d os cil l a t o r s ma k e th e bes t c l o c k s o ur ces. i f th e c l o c k is g e n e ra t e d f r om anot he r t y p e of s o u r c e ( b y g a t i n g , d i v i d i n g , or ot he r m e t h o d s), i t sh ou ld be r e timed b y th e o r ig inal clo c k a t t h e l a st ste p . the ad9289 can als o s u p p o r t a sin g le-en d e d cm os c l o c k. r e f e r t o th e ev a l ua ti o n boa r d sch e ma ti cs t o e n a b le th i s f e a t ur e . pow er dis s i pa tion an d st an db y mo de a s sh o w n in f i g u r e 31, th e p o w e r dis s i p a t ed b y th e ad9289 is prop or t i on a l to it s s a m p l e r a te. t h e d i g i t a l p o we r d i ss ip a t i o n do es n o t va r y b e ca us e i t is d e t e r m in e d p r ima r i l y b y t h e st r e n g t h o f t h e dig i t a l dr i v ers a nd t h e lo ad o n e a ch o u t p ut b i t. dig i t a l p o w e r co n s um pt io n can b e mi nim i z e d b y r e d u cin g t h e ca p a c i t i v e lo ad p r es en t e d t o t h e o u t p u t dr i v ers. the da t a i n f i gur e 31 was c o l l e c t e d w h i l e a 5 pf lo ad was pl ace d on e a ch output d r ive r . the a n alog cir c ui tr y o f th e ad9289 is o p timal l y b i as ed t o achie ve exce l l en t p e r f o r ma n c e w h ile a f fo r d in g r e d u ce d po w e r c o n s u m p t i o n . encode (msps) power ( m w) 600 550 500 450 400 350 curre nt (ma) 180 160 120 100 140 80 60 40 20 0 10 20 40 30 60 50 70 03682-032 i avdd i drvdd power f i gure 31. sup p l y current v s . f sa mple fo r f in = 1 0 . 3 mh z b y as s e r t in g the p d wn p i n hig h , th e ad9289 is p l ace d in st andb y mo de. i n t h is st a t e, t h e a d c ty p i c a l l y diss i p a t e s 7 m w . d u r i n g s t an db y t h e l v ds o u t p u t dr i v ers a r e pl ace d i n a hig h im p e dan c e st a t e. re as s e r t in g t h e p d wn p i n lo w r e t u r n s t h e ad9289 in t o i t s n o r m al o p er a t io nal m o de . i n st andb y mo d e , l o w p o we r diss i p a t ion is achi e v e d b y sh ut t i ng d o w n t h e re f e re nc e, re f e re n c e bu f f e r , and bi a s i n g ne t w or k s . t h e deco u p lin g ca p a ci t o rs o n reft an d refb a r e dis c ha rg ed w h en en t e r i n g st and b y m o de an d t h e n m u st b e r e ch arge d w h en r e t u r n in g t o n o r m a l o p era t io n. a s a r e su lt, t h e wa k e -u p t i me is rel a te d to t h e t i me sp e n t i n st andb y mo de, and shor te r st andb y c y cl e s re su lt i n prop or t i on a l ly shor te r w a ke - u p t i me s . w i t h t h e r e co mmen d e d 0.1 f a nd 10 f deco u p lin g ca p a ci t o rs o n ref t a nd refb , i t ta k e s a p p r o x ima t e l y 1 s t o f u l l y disc ha rg e th e re f e re nc e bu f f e r d e c o up l i ng c a p a c i tor s a n d 7 m s to re store f u l l op e r a t i o n . digital out p uts the ad9289 s dif f er en tial o u t p u t s co nf o r m t o the ans i -644 l v ds st anda rd . t o s e t t h e l v d s b i as c u r r en t pl ace a r e sist o r (rs e t is n o minall y eq ual t o 3.9 k?) t o gr o u n d a t t h e l v ds bi as p i n. the rs et r e sisto r c u r r en t is der i ve d on-ch i p a nd s e ts t h e o u t p u t c u r r en t a t e a c h o u t p u t e q ua l t o a n o minal 3.5 ma. a 100 ? dif f er en tial t e r m ina t ion r e sis t o r p l aced a t t h e l v ds r e cei v er in p u ts r e s u l t s in a n o minal 350 mv s w in g a t t h e r e ce i v er . t o ad j u s t t h e dif f er en t i al sig n al s w i n g, sim p l y cha n g e t h e r e sist o r t o a dif f er en t val u e , as sh o w n in t a b l e 7. ta ble 7. l v ds bia s pi n conf i g ura t i o n rset differentia l output swing 3.6k 375 mv p-p 3.9k (default) 350 mv p-p 4 . 3 k 3 2 5 m v p - p the ad9289 s l v ds o u t p u t s facili t a t e in t e r f acin g wi th l v ds r e cei v ers in c u s t o m a s i c s an d fpga s tha t ha ve l v ds c a p a - b i l i t y f o r s u pe ri o r s w i t c h in g perf o r m a n c e in n o i s y e n v i r o n- m e n t s. sing le p o in t - to -p oin t ne t to p o lo g i es a r e r e co mme n d e d wi t h a 100 ? t e r m ina t io n r e sis t o r p l aced as c l os e t o the r e cei v er a s p o ss i b l e . i t i s re c o m m e nd e d t o k e e p t h e t r a c e l e ng t h no lo n g er t h a n 12 i n ch es and t o k e ep dif f er en t i al ou t p ut t r aces clos e t o g e t h er and a t e q ua l len g t h s. t h e f o r m a t of t h e output d a t a c a n b e s e l e c t e d a s of f s e t bi n a r y or tw os co m p le m e n t . a q u ick exam ple o f e a ch o u t p u t c o di n g fo r m a t ca n b e fo un d in t a b l e 8. the df s p i n is us e d to s e t t h e fo r m a t ( s e e t a bl e 9 ) . tab l e 8. digita l outp ut cod i ng code vin+ ? vin? input span = 2 v p-p (v) vin+ ? vin? input span = 1 v p-p (v) di gi tal ou tp u t offset bin a r y (d7... d0) di gi tal o u tput twos complem e nt (d7... d0) 255 1. 000 0. 500 111 1 1 111 011 1 1 111 128 0 0 100 0 0 000 000 0 0 000 127 ?0. 0 0 781 ?0. 0 0 391 011 1 1 111 111 1 1 111 0 ?1. 00 ?0. 5 0 00 000 0 0 000 100 0 0 000
ad9289 rev. 0 | page 17 of 32 table 9. data format con f iguration dfs mo de data fo rmat a v d d t w o s complem e n t a g n d o f f s e t b i n a r y timing d a t a f r om e a ch a d c i s s e r i a l i z e d a n d prov i d e d on a s e p a r a te c h a n n e l . the da ta ra te f o r eac h se ri al s t r e a m i s eq ual t o ei gh t b i ts tim e s t h e s a m p le c l o c k ra t e , wi t h a maim u m o f 520 mh z (8 b i ts 65 ms ps = 520 mh z). the lo w e s t typ i cal con v ersio n ra t e is 12 ms ps . t w o o u t p u t c l o c ks a r e p r o v ide d t o as sis t in c a p t ur in g da ta f r o m th e ad9289. the d c o is us e d to c l o c k th e o u t p u t da t a an d is eq ual t o f o ur tim e s t h e s a m p lin g c l o c k (cl k ) ra t e . d a ta is c l o c k e d o u t o f t h e ad9289 and ca n be ca p t ur e d o n the r i sin g a nd fa l l in g e d ge s o f t h e d c o t h a t sup p o r ts do ub le- d a t a r a te o p era t ion (d d r ). th e f r am e cl o c k o u t (fc o ) s i g n als t h e st a r t o f a ne w o u t p ut b y t e an d is e q u a l t o t h e s a m p li n g clo c k ra t e . s e e th e tim i n g di a g ra m sh o w n in f i gur e 2 f o r m o r e i n f o rm a t i o n . lock pin the ad9289 con t a i n s an in t e r n al p ll tha t is us ed t o g e n e ra t e t h e d c o . w h en t h e pll is lo ck e d , t h e lo c k sig n al wil l be lo w , indic a t i n g va lid d a t a on t h e o u tp u t s. i f f o r a n y r e as o n the p ll los e s lo c k , th e lo c k s i gn al g o e s h i gh as s o o n as t h e l o ck cir c ui t r y det e c t s an un lo ck e d con d i t io n. w h i l e t h e pll i s unlo ck e d , t h e da t a o u t p u t s and d c o r e ma in s in t h e l a st k n ow n st a t e. i f t h e lo c k s i gn al g o e s h i gh in th e middle o f a b y te, n o da t a o r d c o sig n als wil l b e a v a i la b l e f o r th e r e s t o f t h e b y t e . i t ta k e s a t le as t 1.8 s a t 65 ms ps t o r e ga in lo c k o n c e i t is los t . n o te tha t r e ga inin g lo ck is s a m p le ra te- dep e n d e n t and t a k e s a t le a s t 10 0 in p u t p e r i o d s a f t e r t h e pll acq u ir es t h e in pu t clo c k. on ce t h e p ll rega in s lo ck the d c o sta r ts. the f i rs t valid da ta b y te i s i n di c a te d b y t h e f c o s i g n a l . th e f c o r i s i ng e d ge o c c u rs 0.5 t o 1.5 in p u t c l o c k p e r i o d s a f t e r lo c k go e s l o w . cml pin a co mm o n -m o d e le v e l o u t p u t is a v a i la b l e a t p i n f3. this o u t p u t s e lf b i as es t o a v dd/2. this is a r e l a t i ve ly hig h im p e d a n c e o u t p u t (2. 5 k n o m i n a l ) , wh i c h m a y n eed t o b e co n s i d e r ed w h en us e d as a r e fer e n c e. dtp pin w h en t h e dig i t a l test p a t t er n ( d tp) p i n is ena b l e d (p u l le d to a v dd ) , a l l of t h e a d c ch an n e l output s sh i f t o u t t h e f o l l ow i n g p a t t er n 11000000. th e fc o and d c o o u t p u t s s t il l w o rk as us ual while al l c h a n n e ls s h if t o u t th e t e s t p a t t e r n . this p a t t er n allo w s th e user t o perf o r m ti m i n g ali g nm en t ad u s t m e n t s b e t w e e n th e d c o a n d th e o u t p u t d a ta . voltage r e fe r e nc e a st a b le an d acc u ra t e 0.5 v vol t a g e r e fer e n c e is b u i l t i n t o t h e ad9289. th e in p u t ra n g e ca n b e ad u s t ed b y var y in g th e r e f e r - en c e v o l t a g e a p p l ied t o t h e ad9289, usin g ei ther th e in t e r n al re f e re nc e or an e te r n a l ly a p p l i e d re f e re nc e vo lt age. t h e i n put sp an of t h e a d c t r a c k s re fe re n c e volt age ch an ge s l i ne arly . t h e sh are d re f e re nc e mo d e ( s e e f i g u re 3 2 ) a l l o w s t h e u s e r to et e r n al l y co nne c t t h e r e fer e n c e b u f f ers f r o m t h e quad a d c fo r b e t t er ga in an d o f fs et ma t c hi n g p e r f o r ma n c e . i f t h e ad c s a r e t o fun c ti o n in d e pen d en tl y , th e r e f e r e n c e deco u p li n g ca n be tr e a t e d indep e n d en t l y and can p r o v ide b e t t er is ol a t ion b e tw e e n t h e fo ur ch an nel s . t o e n abl e sh are d re fe re nc e mo d e , t h e sh a r e d _ r e f p i n m u s t b e t i e d hig h an d et e r n al r e fer e n c e b u f f er de co u p lin g p i ns m u st b e e te r n a l ly shor te d. ( r e f t_ a m u s t b e e te r n a l ly shor te d to r e f t _ b a nd r e f b _ a m u st b e s h or te d to r e f b _ b . ) n o te t h a t c h a n n e ls a and b a r e r e fer e n c e d to r e f t _a and ref b _a an d c h a n n e ls c and d a r e r e fer e n c e d to ref t _ b a nd ref b _b . table 10. refer e nce settings selected mode sense voltage resulting v ref (v) resulting diff er enti al sp an (v p-p) ex te rna l refer e nce avd d n / a 2 ex te rna l refer e nce inter n al, 1 v p-p fsr vr e f 0 . 5 1. 0 prog ramm able 0. 2 v t o vref 0. 5 (1 + r2/r1) 2 vref inter n al, 2 v p-p fsr agn d to 0. 2 v 1. 0 2 . 0 i n te rna l re fere nce conne c tion a co m p a r a t o r wi t h in t h e ad9 289 det e c t s t h e p o t e n t ial a t t h e s e ns e pin and co nf igur es t h e refer e n c e i n to fo ur p o ssi b le s t a t es, w h ich a r e s u mma r i ze d i n t a b l e 10. i f s e ns e is g r o u nde d , t h e r e fer e n c e am plif ier s w i t ch is co nne c t e d t o t h e i n t e r n a l r e sis- to r divider (s e e f i gur e 33), s e t t i n g vref to 1 v . c o nn e c t i n g t h e s e ns e pin t o t h e vref p i n s w i t ch es t h e am plif ier o u t p u t t o t h e s e ns e pin, co n f igur in g t h e i n t e r n a l o p a m p cir c ui t as a v o lt a g e f o l l owe r and pr ov i d i n g a 0 . 5 v re f e re nc e output . i f an e te r n a l r e sisto r di vi der is co nne c t e d as sh own i n f i gur e 34 t h e s w i t ch is a g a i n s e t t o t h e s e ns e pin. this p u ts t h e r e fer e n c e a m plif ier i n a no n i n v e r t i ng mo d e w i t h t h e v r e f output d e f i ne d a s ? ? ? ? ? ? + =
ad9289 rev. 0 | page 18 of 32 10 f 0.1 f v ref v ref sense 0.5v control reft_a 0.1 f 0.1 f 10 f 0.1 f refb_a select logic avdd a core b core + v ref vin ?c (?d) shared_ref vin+c (+d) reft_b 0.1 f 0.1 f 10 f refb_b c core d core + 03682-011 vin? a ( ? b) vin+a (+b) f i gure 32. sha r ed r e ferenc e mod e e n a b led 10 f 0.1 f v ref v ref sense 0.5v control reft_a 0.1 f 0.1 f 10 f 0.1 f refb_a select logic a core b core + v ref shared_ref reft_b 0.1 f 0.1 f 10 f refb_b c core d core + 03682-012 vin? c ( ? d) vin+c (+d) vin ?a ( ? b) vin+a (+b) f i gure 33. inte rn al r e fer e n c e configu r atio n 10 f 0.1 f v ref v ref sense 0.5v r2 r1 control reft_a 0.1 f 0.1 f 10 f 0.1 f refb_a select logic a core b core + v ref shared_ref reft_b 0.1 f 0.1 f 10 f refb_b c core d core + 03682-013 vin ?c (?d) vin+c (+d) vin?a ( ? b) vin+a (+b) f i g u re 34. p r og r a m m ab le r e f e rence conf ig ur at i o n i f th e in t e r n al ref e r e n c e o f the ad9289 is us ed t o dr i v e m u l t i p le c o n v e r te rs to i m prove g a i n m a tch i ng , t h e l o a d i n g of t h e re fe r - en c e b y t h e o t her co n v er t e rs m u s t b e con s ider e d . f i gur e 35 dep i c t s h o w t h e in t e r n a l r e fer e nce v o l t a g e is a f fe c t e d b y lo ading. i load (ma) v re f e rror (%) 0.05 0 ?0.15 ?0.10 ?0.05 ?0.20 ?0.25 ?0.30 ?0.35 ?0.40 0 1.0 0.5 2.0 1.5 2.5 03682-033 v ref = 0.5v v ref = 1.0v f i gure 3 5 . vref a c cur a c y vs . l o a d
ad9289 rev. 0 | page 19 of 32 extern al r e f e r e nc e ope r atio n the us e o f a n e x t e r n al r e fer e n c e ma y b e n e ces s a r y t o enha n c e t h e ga i n acc u rac y o f t h e ad c o r im p r o v e t h er mal dr if t char ac te r i st ic s . f i g u re 3 6 shows t h e ty p i c a l dr if t char ac te r i st ic s o f th e in t e r n al sha r ed r e f e r e n c e in bo th 1 v and 0.5 v m o des. temperature ( c) v re f e rror (%) 0.15 0.10 0 0.05 ?0.05 ?0.10 ?0.15 ?0.20 ?0.25 ?4 0 0 ?20 6 0 40 20 80 03682-034 v ref = 0.5v v ref = 1.0v f i g u re 36. t y pic a l v r e f d r if t w h en t h e s e nse p i n is t i e d t o a v d d , t h e i n te r n al r e fer e n c e is dis a b l e d , al lo wi n g t h e us e o f a n ext e r n al r e fer e n c e . a n i n t e r n al r e fer e n c e b u f f er lo ads t h e ext e r n al r e fer e n c e wi t h a n e q ui vale n t 7 k? lo ad . the i n t e r n al b u f f er s t il l g e n e r a t e s t h e p o si t i v e and n e g a t i ve f u l l -s c a le r e fer e n c es, r e f t _a and re f t _b an d refb_a an d r e fb_b , fo r t h e ad c co r e . the in p u t s p a n is al wa ys t w ic e t h e val u e o f t h e r e fer e n c e v o l t a g e; t h er efo r e , t h e e x te r n a l re f e re nc e m u st b e l i m i t e d to a m a x i m u m of 1 v . power and ground recommendations w h en connec t in g p o w e r t o th e ad9289, i t is r e co mm en de d tha t tw o s e p a ra t e 3.0 v s u p p lies b e us e d . o n e fo r a n alog (a vd d) a nd on e f o r dig i tal (d r v d d ). i f o n l y o n e su p p ly is a v a i lab l e th en i t s h o u ld b e r o u t ed t o th e a v d d f i r s t a n d ta p p ed o f f a n d is ola t e d w i t h a fer r i t e b e ad o r f i l t er ch ok e w i t h de co u p lin g ca p a c i t o rs p r o c e e d i n g. o n e ma y wa n t t o us e s e v e ral dif f er en t deco u p lin g ca p a ci t o rs t o co v e r bo th hig h an d l o w f r eq uen c ies. th e s e sh o u ld b e lo ca t e d clos e t h e p o in t o f en t r y a t t h e p c b o a r d le vel as w e l l as clos e t o t h e p a r t s wi t h mi nima l t r ace len g t h . a s i ng l e p c b o a r d g r ou nd p l a n e shou l d b e su f f i c i e n t w h e n u s i n g th e ad9289. w i th p r o p er deco u p lin g an d sma r t p a r t i t io nin g o f th e pc boa r d s a n alog, d i gi tal , a n d c l oc k secti o n s , o p ti m u m pe rf o r m a n c e i s ea s i l y a c h i ev ed .
ad9289 rev. 0 | page 20 of 32 evaluation board the ad9289 e v al ua t i o n bo a r d p r o v ides al l o f th e su p p o r t cir - c u i t r y r e q u ir e d t o o p era t e t h e a d c in i t s v a r i o u s m o des an d co nf igur a t io n s . the con v er ter c a n b e dr i v e n dif f er en t i a l ly thr o ug h a tra n sf o r m e r (defa u l t ) o r th e ad8351 dr i v er . p r o v i- sio n s ha v e als o be e n made t o dr i v e th e ad c sin g le-e n d e d . s e p a ra te p o w e r p i n s a r e p r o v ide d t o is ol a t e t h e d u t f r o m t h e su p p o r t cir c ui t r y . e a ch in p u t conf igura t io n ca n b e s e le c t e d b y p r o p er co nne c t i o n o f va r i o u s j u m p ers (r efer t o t h e s c h e ma t i cs). f i g u re 3 7 show s t h e t y pi c a l b e n c h ch ar a c te r i z a t i on s e tup u s e d t o eval ua t e t h e ac p e r f o r ma n c e o f th e ad9289. i t is cr i t ical tha t t h e sig n al s o ur c e s t h a t a r e us e d ha v e v e r y lo w phas e n o is e ( < 1 p s r m s ji tte r ) to re a l i z e t h e u l t i ma te p e r f or manc e of t h e co n v er t e r . p r o p er f i l t er in g o f t h e a n alog in p u t sig n al t o r e m o ve ha r m o n ics a nd lo w e r t h e in teg r a t e d o r b r o a d b and n o is e a t t h e in pu t is a l s o n e ce ss a r y t o achie v e t h e sp e c if ie d noi s e p e r f or m a nc e . s e e f i gur e 37 t o f i gur e 47 f o r c o m p let e s c h e ma tics an d l a yo u t plo t s, w h ich d e m o nst r a t e t h e r o u t in g and g r o u n d in g te chni q u es tha t sh o u ld be a p p l ie d a t t h e syst em l e v e l . rohde and schwarz, smhu, 2v p-p signal synthesizer rohde and schwarz, smhu, 2v p-p signal synthesizer band-pass filter 3.0v ?+ ? + ?+ 3.3v dut_ a v d d dut_ drv dd gnd gnd brd_ av dd xfmr input clk cha? chd 8-bit serial lvds 2 ch 8-bit parallel cmos usb connection ad9289 evaluation board hsc-adc-fpga high-speed de-serialization board 03682-002 hsc-adc-eval-dc fifo data capture board pc running adc analyzer 3.0v f i g u re 37. ev aluat i on b o a r d conn ec t i ons
ad9289 rev. 0 | page 21 of 32 1 2 r26 dnp u5 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 dco dco fco fco cha cha chb chb chc chc chd chd r25 dnp r67 dnp r2 dnp r3 dnp r4 dnp j6 4 6 5 3 1 2 brd_av dd u7 ad9289 dnc dnc d1 ? a d1+ a fco ? fco+ dnc dnc vi n ? a vi n + a vi n _ a vi n _ a cha cha fco fco dut_av d d agnd agnd vi n + b vi n ? b av dd agnd vi n _ b vi n _ b lv ds bias cml s hare d_re f sen se vr ef av dd agnd re fb_a f7 g7 vr ef s hare d_re f dut_av d d g4 reft_ a f4 re fb_b g5 reft_ b f5 agnd e3 h4 h5 g3 h1 f3 d1+ d d1 ? d dnc dnc pd wn clk+ clk ? dfs c8 d8 c7 vi n ? d f8 vi n + d vi n _ d vi n _ d chd chd dut_av d d g8 agnd d7 agnd e7 vi n + c h7 vi n ? c h6 av dd e4 agnd e5 a8 e8 b8 b7 a7 c1 d2 d1 f1 g1 e1 e2 h2 h3 f2 g2 b1 c2 a1 a2 b2 vi n _ c vi n _ c agnd g6 agnd f6 tp3 av dd e6 tp1 dtp h8 r76 3.9k ? tp2 drv dd drgnd d1+ b d1 ? b dnc dnc lock dco+ a4 d4 dco chb chb dut_drv dd c4 dco ? c5 agnd dco d5 d1+ c chc chc dut_drv dd b5 d1 ? c a5 a3 b4 b3 c3 d6 dnc b6 dnc a6 drv dd c6 drgnd d3 tp9 digital lvds outputs c35 0.1 f c120 10 f c44 0.1 f c1 0.1 f c600 0.1 f c100 10 f c80 0.1 f c250 0.1 f jp 3 jp 5 re mov e cx w h e n us ing e x t e rnal v re f u6 u1 7 u6 v re f = 0.5v trim/nc adr5 1 0 v re f = e x t e rnal v re f = 0.5v ( 1 + ra/rb) v re f = 1 v 5 6 8 7 4 3 1 2 r1 1k ? jp 2 c47 0.1 f cx 10 f brd_av dd nc c53 0.1 f ra dnp rb dnp brd_av dd vr ef v o ltage re fe re nce circuitry u2 1 2 3 4 8 7 6 5 jp 35 brd_av dd vc c din dnc gnd dout ? dout+ dnc dnc p5 r41 50 ? clock inp u t c6 0.1 f tp4 r73 100 ? c7 0.1 f s hare d_re f r102 22 ? s i ngle - e nde d clock driv e r op tion r66 0 ? fin 1017m r71 0 ? u1 12 u1 13 12 jp 9 c36 0.1 f brd_av dd r43 1k ? r40 1k ? brd_av dd r109 1k ? r110 1k ? brd_av dd r70 1k ? r29 1k ? r32 10k ? r72 10k ? r75 10k ? dut_av d d jp 1 r37 10k ? dut_av d d ** dnp p l ace o n l y w h e n us ing t h e ad8351 a s i n pu t. see d a t a s h eet for d e ta i l s. = do not populate = gn d 03682-048 v+ 3 2 1 v? ad9289 e x t e rnal re fe re nce op tion f i g u re 38. ev aluat i on b o a r d s c h e m a t i c , du t , v r e f , and c l o c k input s
ad9289 rev. 0 | page 22 of 32 r1 5 50 ? r 62** dnp jp18 amp _ in1 jp19 jp29 jp20 r3 0 50 ? r 63** dnp jp24 jp21 amp _ in2 r8 3 50 ? r 64** dnp jp27 jp25 amp _ in3 jp26 c2 0.1 f p1 p4 p3 p2 r4 2 50 ? r 65** dnp jp28 amp _ in4 03682-047 c4 0.1 f av dd r1 3 1k ? r 74** dnp r 69** dnp r2 7 33 ? cm2 cm2 4 5 6 3 2 1 r1 6 1k ? c1 5 0.1 f c1 7 dnp c3 0.1 f ch_ b ch_ b l19 120nh l6 120nh l20 120nh r2 3 33 ? c2 1 20pf c2 2 dnp vin _ b vin _ b t2 c2 4 dnp l9 120nh av dd r1 2 1k ? r 59** dnp r 68** dnp r3 1 33 ? cm1 cm1 6 5 4 1 2 3 r2 0 1k ? c1 6 0.1 f c3 1 dnp ch_ a ch_ a l2 120nh l3 120nh l1 120nh r3 4 33 ? c3 0 20pf c2 3 dnp vin _ a vin _ a t1 c1 9 dnp l4 120nh av dd r1 8 1k ? r 77** dnp r 80** dnp r4 7 33 ? cm3 cm3 6 5 4 1 2 3 r1 9 1k ? c1 8 0.1 f c4 2 dnp ch_ c ch_ c l21 120nh l12 120nh l22 120nh r4 4 33 ? c4 1 20pf c4 3 dnp vin _ c vin _ c t3 c2 5 dnp l11 120nh av dd r2 1 1k ? r 84** dnp r 82** dnp r1 4 33 ? cm4 cm4 4 5 6 3 2 1 r2 4 1k ? c2 0 0.1 f c9 dnp c5 0.1 f ch_ d ch_ d l27 120nh l10 120nh l28 120nh r1 1 33 ? c1 0 20pf c1 3 dnp vin _ d vin _ d t4 c2 8 dnp l13 120nh analog input channe l a analog input channe l b analog input channe lc analog input channe l d ** dnp pla c e on ly w h en u s in g th e a d 8351 a s in pu t. see datas he e t for de tails . = do not populate = g n d f i g u re 39. ev aluat i on b o a r d s c h e m a t i c , du t a n a l og inpu t
ad9289 rev. 0 | page 23 of 32 u7 1 2 3 4 10 9 8 7 pw u p rgp 1 inhi inlo 5 rgp 2 voc m r4 8 0 ? r5 0 1k ? c5 2 0.1 f c4 9 0.1 f vpos ophi oplo 6 comm ad8351 r3 5 1.2k ? r6 * dnp * to e nable the p o we r down op tion on the a d 8351, pla c e a 0 ? resistor in this place holder. for p w dn p l ace r6 ad8351 analog input driver option ch_ a r4 8 0 ? c5 1 0.1 f ch_ a r5 10 ? c5 4 0.1 f r7 10 ? c5 0 0.1 f r2 2 25 ? r3 8 50 ? r4 9 25 ? r4 5 1k ? r3 6 10k ? c4 8 0.1 f u9 1 2 3 4 10 9 8 7 pw u p rgp 1 inhi inlo 5 rgp 2 voc m r9 8 0 ? r9 3 1k ? c6 6 0.1 f c6 3 0.1 f vpos ophi oplo 6 comm ad8351 r8 1 1.2k ? r 78* dnp for p w dn p l ace r7 8 ch_ c r9 9 0 ? c6 7 0.1 f ch_ c r8 10 ? c6 5 0.1 f r9 10 ? c6 4 0.1 f r7 9 25 ? r9 1 50 ? r9 2 25 ? r9 4 1k ? r9 0 10k ? c6 2 0.1 f amp _ in3 amp _ in1 u8 1 2 3 4 10 9 8 7 pw u p rgp 1 inhi inlo 5 rgp 2 voc m r6 0 0 ? r5 7 1k ? c6 0 0.1 f c5 7 0.1 f vpos ophi oplo 6 comm ad8351 r5 3 1.2k ? r 51* dnp for p w dn p l ace r5 1 ch_ b amp _ in2 r6 1 0 ? c6 1 0.1 f ch_ b r1 0 10 ? c5 9 0.1 f r1 7 10 ? c5 8 0.1 f r5 2 25 ? r5 5 25 ? r5 6 50 ? r5 8 1k ? r5 4 10k ? c5 5 0.1 f amp _ in4 brd_ av dd brd_ av dd u10 1 2 3 4 10 9 8 7 pw u p rgp 1 inhi inlo 5 rgp 2 voc m r 113 0 ? r 108 1k ? c7 2 0.1 f c6 9 0.1 f vpos ophi oplo 6 comm ad8351 r 103 1.2k ? r 100* dnp for p w dn p l ace r1 0 0 ch_ d r 114 0 ? c7 3 0.1 f ch_ d r3 3 10 ? c7 1 0.1 f r3 9 10 ? c7 0 0.1 f r 101 25 ? r 106 25 ? r 107 50 ? r 111 1k ? r 104 10k ? c6 8 0.1 f brd_ av dd brd_ av dd 03682-049 f i g u re 40. ev aluat i on b o a r d s c h e m a t i c , o p t i on al du t a n al og input d r ive
ad9289 rev. 0 | page 24 of 32 c2 9 0.1 f c2 5 0.1 f brd_ av dd c4 0 0.1 f c1 1 0.1 f dut_ drv dd 03682-050 c1 4 0.1 f c1 2 0.1 f dut_ a v d d c3 7 0.1 f u1 34 u1 56 u1 98 u1 11 10 tp14 tp15 tp16 tp18 unus e d gate s ground te s t p o ints de coup ling cap s c 176 10 f l7 10 h + c 183 0.1 f dut_ a v d d c 171 10 f l8 10 h + c 110 0.1 f dut_ drv dd c 170 10 f l5 10 h + c 108 0.1 f brd_ av dd p6 p1 p2 p3 p4 p5 p6 6 jp1 jp4 jp2 4 5 3 1 2 +3 . 0 v +3 . 0 v +3 . 3 v p o we r conne ctions ** dnp pla c e on ly w h en u s in g th e a d 8351 a s in pu t. see datas he e t for de tails . = do not populate = g n d f i g u re 41. ev aluat i on b o a r d s c h e m a t i c , p o wer , a n d d eco upling
ad9289 rev. 0 | page 25 of 32 03682-036 f i g u re 42. ev aluat i on b o a r d l a yout , pri m ar y s i de 03682-038 f i g u re 43. ev aluat i on b o a r d l a yout , pri m ar y s i de ( w it h gr ou nd co p p e r p o ur)
ad9289 rev. 0 | page 26 of 32 03682-039 f i g u re 44. ev aluat i on b o a r d l a yout , g r ou nd p l ane 03682-040 f i g u re 45. ev aluat i on b o a r d l a yout , p o we r p l an e
ad9289 rev. 0 | page 27 of 32 03682-045 f i g u re 46. ev aluat i on b o a r d l a yout , s e c o nd ar y s i de 03682-041 f i g u re 47. ev aluat i on b o a r d l a yout , s e c o nd ar y s i de ( w it h ground cop p er p o ur)
ad9289 rev. 0 | page 28 of 32 table 11. evaluation board bill of materials (bom) item qnty. per board refdes device package value manufacturing mfg. part number 1 1 ad9289 bga reva/pcb pcb pcb pcb pcsm pcsm 2 1 assembly protronics protronics 3 8 r46, r48, r60, r61, r98, r99, r113, r114 res_402 402 0 yageo america 9c04021a0r00jlhf3 4 8 r5, r7, r8, r9, r10, r17, r33, r39 res_402 402 10 susumu co ltd rr0510r-100-d 5 8 r22,r49, r52, r55, r79, r92, r101, r106 res_402 402 25 susumu co ltd rr0510r-240-d 6 8 r11,r14, r23, r27, r31, r34, r44, r47 res_402 402 33 susumu co ltd rr0510r-330-d 7 4 r38, r56, r91, r107 res_402 402 50 panasonic-ecg erj-l14kf50mu 8 1 r73 res_402 402 100 yageo america 9c04021a1000flhf3 9 8 r45, r50, r57, r58, r93, r94, r108, r111 res_402 402 1k panasonic-ecg erj-2gej102x 10 4 r35, r53, r81, r103 res_402 402 1.2k panasonic-ecg erj-2gej122x 11 13 r6, r32, r36, r51, r54, r72, r75, r78, r90, r100, r104, r37, r76 res_402 402 10k susumu co ltd rr0510p-103-d 12 6 r62, r63, r64, r65, r66, r71 bres603 603 0 panasonic-ecg erj-3gey0r00v 13 1 r102 bres603 603 22 susumu co ltd rr0816q-220-d 14 5 r15, r30, r41, r42, r83 bres603 603 50 susumu co ltd rr0816q-49r9-d-68r 15 23 r1, r12, r13, r16, r18, r19, r20, r21, r24, r29, r40, r43, r59, r68, r69, r70, r74, r77, r80, r82, r84, r109, r110 bres603 603 1k susumu co ltd rr0816p-102-d 16 2 r96, r97 bres603 603 xxx 17 4 c10, c21, c30, c41 cap402 402 20pf kemet c0402c220j5gactu 18 36 c1, c35, c44, c47, c80, c250, c600, c11, c12, c14, c37, c40, c48, c63, c64, c65, c66, c67, c68, c69, c70, c71, c72, c73 cap402 402 1uf panasonic-ecg ecj-0ef1c104z 19 17 c2, c3, c4, bypasscap 603 0.1uf kemet c0603c104z3vactu c5, c6, c7, c15, c16, c18, c20, c25, c29, c36, c53, c108, c110, c183 20 3 c100, c120, c163 tantalumb 805 10uf panasonic-ecg ecj-2fb0j106m 21 3 c170, c171, c176 tantalumb t491b06k01 10uf kemet t491b106k016as 22 16 l1, l2 ,l3, l4, l6, l9, l10, l11, l12, l13, l19, l20, l21, l22, l27, l28 inductor_6 603 120nh murata blm18bb750sn1d 23 3 l5,l7,l8 ind1210 1210 10uh panasonic-ecg elj-sa100kf 24 1 p6 ptmicro6 ptmicro6 6-pole pcb header wieland z5.531.3625.0
ad9289 rev. 0 | page 29 of 32 item qnty. per board refdes device package value manufacturing mfg. part number 1 6-pole pcb connector wieland 25.600.5653.0 25 5 p1, p2, p3, p4, p5 smbmst smb smbmst amphenol-rf division 901-144-8rfx 26 4 t1, t2, t3, t4 adt1-1wt cd542_x65 adt1-1wt minicircuits adt1-1wt 27 1 u17 header 2mmsmt-872 wm18158- nd molex/waldom electronics corp 87267-0850 28 1 u5 diff_conn fcn_268m01 diff_conn fujitsu fcn-268m012-g/1d 29 1 j6 minijmpr3 2mmsmt-872 minijmpr3 molex/waldom electronics corp 87267-0850 30 2 jp1, jp2 sgljmpr sgljmpr 87267-0850 samtec tsw-120-07-g-s 31 2 11/4" standoff nylon 1/4" 6-32 raf 4040-632-n 32 2 6-32nuts nylon 6-32 raf 3058-n 33 1 u1 74vhc04mtc tssop-14 74vhc04 fairchild semiconductor 74vhc04mtc 34 1 u2 fin1017m mo8a_(soic) fin1017m fairchild semiconductor fin1017m 35 1 u4 ad9289bbc- 65 9289bga 9289bga adi ad9289bbc-65 36 1 u6 adr510 sot23 adr510 adi adr510 37 4 u7, u8, u9, u10 ad8351arm msop010 ad8351 adi ad8351arm
ad9289 rev. 0 | page 30 of 32 outline dimensions compliant to jedec standards mo-205-ba a bo t tom view 87 65 4 3 21 5.60 bsc sq 0.80 bsc a 1 corne r index area top view seating plane detail a ball diameter 0.34 nom 0.25 min 0.55 0.50 0.45 coplanarity 0.12 1.31 1.21 1.10 8.00 bsc sq ball a1 indicator detail a 1.70 1.55 1.35 b c d e f g h f i g u re 48. 6 4 -l ead chip s c a l e p a ckag e ba ll g r id a r r a y [cs p _bg a ] (bc-64- 1) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ad9289bbc C40c to +85c 64-lead chip scale package ball grid array [csp _bga] bc-64-1 a d 9 2 8 9 - 6 5 e b evaluation boar d
ad9289 rev. 0 | page 31 of 32 notes
ad9289 rev. 0 | page 32 of 32 notes ? 2004 a n alo g de vices, inc. all rig h ts reserv ed. tra d em arks an d registered tra d emar ks are the prop erty of their respective owners . d03682-0-10/04(0)

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